1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit (IC) device, and more particularly, to a semiconductor IC device and a data output method of the same.
2. Related Art
FIG. 1 is a schematic block diagram of a conventional semiconductor IC device. In FIG. 1, a semiconductor IC device includes an internal clock generator 11, a Delayed Locked Loop (DLL) 12, a flip-flop 13, a core block 14, an input/output sense amplifier IOSA 15, a pipe latch 16, a data selector 17, a domain crossing block 18, and a read controller 19. Here, the semiconductor IC device can be classified as being one of an internal clock domain, i.e., a circuit area operating according to an internal clock signal ‘INT_CLK’, and one of a DLL clock domain, i.e., a circuit area operating according to a DLL clock signal ‘DLL_CLK’.
The internal clock domain includes a flip-flop 13, a core block 14, and an IOSA 15. The DLL clock domain includes a pipe latch 16, a data selector 17, and a read controller 19. The internal clock generator 11 generates an internal clock signal ‘INT_CLK’ by using an external clock signal ‘EXT_CLK’, and generates a DLL clock signal ‘DLL_CLK’ by using the external clock signal ‘EXT_CLK’.
The domain crossing block 18 performs an operation to transform a control operation according to a timing of the internal clock signal ‘INT_CLK’ to that according to a timing of the DLL clock signal ‘DLL_CLK’. According to the DLL clock signal ‘DLL_CLK’, the read controller 19 generates various control signals, such as ‘PINZ<0:N>’, ‘PROUT<0:N>’, ‘RDOUT’, ‘FDOUT’, ‘RCLK_DO’, and ‘FCLK_DO’, to control the pipe latch 16 and the data selector 17. According to the various control signals, such as ‘PINZ<0:N>’, ‘PROUT<0:N>’, ‘RDOUT’, ‘FDOUT’, ‘RCLK_DO’, and ‘FCLK_DO’, both the pipe latch 16 and the data selector 17 line up parallel data output from the core block 14 and output them in a predetermined order.
In order to synchronize data with a CAS latency and an external clock signal according to an external read command, applications, up to now, have used a DLL clock signal. However, various applications now require output data as soon as possible after an external read command. Thus, in order to meet the requirement of producing data as soon as possible after an external read command, current semiconductor IC devices have problems of greatly modifying circuit structures to meet the requirement that are complicated and occupy large lay-out areas, such as a DLL 12, a domain crossing block 18, and a read controller 19, for controlling both a pipe latch 16 and a data selector 17 according to a DLL clock signal.